Robustness Optimization in Subthreshold Circuits

Emerging IC applications such as wireless sensor nodes, RFIDs, and medical devices place increasing emphasis on low energy operation instead of performance. Subthreshold circuits operate with a power supply set below the transistor voltage threshold and thus offer significant power reduction, while operating at frequencies in the range of a few MHz. A number of designs have successfully been presented [1, 2, 3]. However, they rely on leakage currents that are exponentially dependent on Vt and thus subthreshold designs have dramatically increased sensitivity to process variations [3]. B Zhai, et al address the mitigation of variability in subthreshold designs by providing statistical models for energy and delay that consider the impact of process variations [4]. B. Calhoun suggests that minimumsized circuits would minimize energy per operation [5]. J. Kwong, et al suggest that design yield-based upsizing is necessary to achieve robustness at lowered supply voltages [6].